1. Field of the Invention
This invention relates to the field of integrated chip design, and in particular to methods for solving the problem of increased interconnect delays resulting from reduced chip geometry.
2. Description of the Related Art
Interconnect propagation delays are a serious issue for next generation microprocessors. Interconnect delays do not scale with technology. Rather, the delays actually increase with shrinking geometries due to fringing effects. The delays are playing an increasingly significant role in the determination of overall system performance. In many cases the propagation delay plays a critical role in the chip design cycle. Consequently more resources are being dedicated to the determination and minimization of interconnect delay.
The determination of interconnect propagation delay is based on interconnect resistivity, capacitive coupling, and geometry. Since the resistivity varies with the layer of the interconnect (i.e. polysilicon, metal I, metal II, etc.), the capacitive coupling is determined by proximity to other interconnects, and geometry exerts a non-linear effect on propagation delay, the determination of delay is a problem of significant complexity. When it is taken into account that many millions of interconnects must be evaluated, the problem becomes a significant obstacle to next-generation microprocessor design.
It is therefore desirable that a method be found for simplifying the determination of interconnect propagation delay. It is further desirable that the propagation delay be optimized in order to maximize microprocessor performance.